`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/07/07 21:54:15
// Design Name:
// Module Name: clk_input
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////


module clk_input (
	input  clk_p,
	input  clk_n,
	output clk
);

	IBUFDS #(
		.DIFF_TERM   ("TRUE"   ), // Differential Termination
		.IBUF_LOW_PWR("TRUE"   ), // Low power="TRUE", Highest performance="FALSE"
		.IOSTANDARD  ("LVDS_25")  // Specify the input I/O standard
	) IBUFDS_inst_adcclk (
		.O (clk  ), // Buffer output
		.I (clk_p), // Diff_p buffer input (connect directly to top-level port)
		.IB(clk_n)  // Diff_n buffer input (connect directly to top-level port)
	);
endmodule
